The subject invention relates to data communication apparatus and, more particularly, to an improved circuit for adjusting the timing of a sampling clock typically used to recover data in the receiver of a data modem. Precise adjustment of the sampling clock is essential to optimum recovery of data.
In the prior art, it has been suggested to derive a clock correction signal by correlating so-called main channel error signals and derivative channel signals. The derivative channel signal is derived by differentiating the main channel (received) signal. According to this suggestion, the derivative channel signals must be determined every baud interval and must be equalized by a second equalizer identical to the equalizer employed to equalize the main channel signal. Furthermore, the technique assumes that the sampling clock has already been set to near the correct sampling point. While theoretically interesting, this prior art technique has not appeared practically implementable because of the complexity involved, such as in providing a second equalizer identical to that utilized to equalize the received signal. The prior art technique proves particularly undesirable in modems employing microprocessor techniques because of the excessive number of operations required, which waste valuable microprocessor computation power.